A semiconductor integrated circuit including an oscillator conventionally will use an external power supply voltage to provide power to the oscillator. However, another conventional approach is to use a regulated voltage to provide power to an oscillator to reduce power consumption.
A reset disables the oscillator. However, when a reset is terminated or cancelled, conventionally, it is necessary for an oscillator to operate for a sufficient time period (initialization time period) after the cancellation of the reset. Such an initialization time period can allow an oscillating element to provide an oscillation signal to grow, in order to be large enough for proper operation. This initialization time period is conventionally ensured by using a clock of the oscillator per se, or by using an exclusive counter.
However, another conventional approach of ensuring the proper initialization time period is by using an external capacitor and resister to provide an RC time constant.
A conventional clock generating circuit is disclosed in Japanese Patent Application Laid-Open 8-204450 (JP 8-204450 A) and will be explained with reference to FIGS. 9 and 10. Referring to FIG. 9, a circuit schematic diagram of a conventional clock generating circuit is set forth and given the general reference character 900. FIG. 10 is a timing diagram showing the operation of conventional clock generating circuit 900 in a power up. Power up may occur when power is initially applied to a device, or after a reset.
Referring to FIG. 9, conventional clock generating-circuit 900 includes an oscillating circuit 910, a constant voltage generating circuit 920, a level conversion circuit 930, and a logic circuit 940.
Constant voltage generating circuit 920 includes a voltage regulator 922 and a switching means 924. Switching means 924 switches an operation power supply voltage VOSC supplied to oscillating circuit 910 in accordance with a start control signal (START CONTROL SIGNAL) pulse width. Such a pulse may be generated upon power up and, ideally, terminate some time after the oscillating circuit 910 provides a stable oscillation OSCCLK1.
Referring now to FIG. 10 in conjunction with FIG. 9, when start control signal is logic high, a power supply voltage VDD is provided as the operation power supply voltage VOSC of oscillating circuit 910. After oscillation stabilization, start control signal (START CONTROL SIGNAL) transitions to a low level and switching means 924 provides a constant voltage from voltage regulator 922 as operation power supply voltage VOSC of oscillating circuit 910. In this way, the operation power supply voltage VOSC of oscillating circuit 910 can be reduced during the operation of logic circuit 940 and power consumption during normal operation of a semiconductor integrated circuit may be reduced.
Another conventional clock generating circuit is disclosed in Japanese Patent Application Laid-Open 10-004347 (JP 10-004347 A) and will be explained with reference to FIGS. 11 and 12. Referring to FIG. 11, a circuit schematic diagram of a conventional clock generating circuit is set forth and given the general reference character 1100. FIG. 12 is a timing diagram showing the operation of conventional clock generating circuit 1100 after a reset.
Conventional clock generating circuit 1100 includes an oscillating circuit 1110, a counter 1120, and a RC oscillator 1130. RC oscillator 1130 becomes stable in a much shorter time period and has a much larger oscillation period than oscillating circuit 1110.
Referring now to FIG. 12 in conjunction with FIG. 11, after clock stop signal S1 goes low, oscillating circuit 1110 and RC oscillator 1130 provide oscillating signals (S2 and S3), respectively. Buffer circuit 1140 provides an output S4 that transitions when oscillating signal S2 reaches input levels (VH and VL). Counter 1120 counts the number of cycles of output S4 during a logic high period of oscillating signal S3 provided from RC oscillator 1130 as a reset input to counter 1120. If the number of cycles counted by counter 1120 becomes a predetermined number (in this case, such that counter output signals S5 to S8 are all high), the oscillating circuit 1110 is determined to be stabilized. After the oscillating circuit is stabilized such that buffer 1140 provides a predetermined frequency, latch 1150 provides an output S9 that is logic high and AND gate 1160 is enabled to provide a clock signal S10.
Another conventional clock generating circuit is disclosed in Japanese Patent Application Laid-Open 2000-293258 (JP 2000-293258 A) and will be explained with reference to FIGS. 13 and 14. Referring to FIG. 13, a circuit schematic diagram of a conventional clock generating circuit is set forth and given the general reference character 1300. FIG. 14 is a timing diagram showing the operation of conventional clock generating circuit 1300 after a reset.
Conventional clock generating circuit 1300 includes an oscillating circuit 1310, counters (1320 and 1330), a judging circuit 1340, a clock generating circuit 1350, a buffer 1302, and an inverter 1303.
Referring now to FIG. 14 in conjunction with FIG. 13, buffer 1302 detects the positive edge of an output signal 702 of oscillating circuit 1310 and has a high threshold value. Inverter 1303 detects the negative edge of output signal 702 of oscillating circuit 1310 and has a low threshold value. Counter 1320 counts the clock cycles provided by buffer 1302 and counter 1330 counts the clock cycles provided by inverter 1303. After N-1 counts, the values of counters (1320 and 1330) are coincidence, a N-1 coincidence signal (internal to judging circuit 1340 and not illustrated in FIG. 13) is generated and judging circuit 1340 generates a permission signal 709. In response to permission signal 709, clock generating circuit 1350 provides a clock output based on output signal 702 of oscillating circuit 1310. After N counts by either counter (1320 or 1330), the values of counters (1320 and 1330) are reset by a N signal 705 provided by judging circuit 1340. At this time, if N-1 coincidence signal has not been generated, permission signal 709 is reset (or not generated). In this way, a clock signal is not provided until an output signal 702 of an oscillating circuit 1310 has provided N-1 cycles with both a minimum and a maximum voltage value so that the oscillating circuit 1310 is judged to be stabilized.
Another conventional clock generating circuit is used in an 8-bit single chip microcomputer 78K0 and 78K0/s series by Nippon Denki (NEC) and will be explained with reference to FIGS. 15 and 16. Referring to FIG. 15, a circuit schematic diagram of a conventional clock generating circuit is set forth and given the general reference character 1500. FIG. 16 is a timing diagram showing the operation of conventional clock generating circuit 1500 after a reset.
Conventional clock generating circuit 1500 includes an oscillating circuit 1510, a clock output circuit 1520, and a logic circuit 1530. An exclusive counter 1522 in clock output circuit 1520 counts the oscillation clock OSCCLK1 provided by oscillating circuit 1510 after a reset is cancelled (reset signal RESET goes high as seen in FIG. 16). When the count value in exclusive counter 1522 reaches a predetermined value, a count signal CNT1 becomes high and an output Q is provided by a flip-flop circuit 1524 in clock output circuit 1520. In this way, AND gate 1526 in clock output circuit 1520 is enabled to provide a clock signal CLK based on the oscillation clock OSCCLK1 provided by oscillating circuit 1510.
Another conventional clock generating circuit is used in a μPD780955/μPD780958 single chip microcontroller by Nippon Denki (NEC) and will be explained with reference to FIGS. 17 and 18. Referring to FIG. 17, a circuit schematic diagram of a conventional clock generating circuit is set forth and given the general reference character 1700. FIG. 18 is a timing diagram showing the operation of conventional clock generating circuit 1700 after a reset.
Conventional clock generating circuit 1700 differs from conventional clock generating circuit 1500 in that reset signal RESET is generated by an RC circuit 1710. Reset signal RESET is provided to a constant voltage generating circuit 1720. Constant voltage generating circuit 1720 includes a voltage regulator 1722 and a switching means 1724. When reset signal RESET is low, a power supply of voltage VDD is provided to the oscillation circuit 1730 and logic circuit 1740. However after reset signal RESET becomes logic high, a regulator voltage output provided by voltage regulator 1722 is provided to the oscillation circuit 1730 and logic circuit and logic circuit 1740. Thus, the operation voltage is switched after oscillation circuit 1730 is stabilized.
In conventional clock generating circuit 1500 of FIG. 15, current consumption may be increased because logic circuit 1530 and oscillation circuit 1510 are always operated by an external power supply voltage VDD after power is turned on.
In conventional clock generating circuit 900, the oscillating circuit 910 is operated by the voltage provided by voltage regulator 922 when the oscillating circuit 910 provides a stabile oscillation. In this way, power consumption may be reduced. However, because a variation can occur in the time necessary for the oscillating circuit 910 to stabilize, the start control signal START CONTROL SIGNAL may end prior to sufficient stabilization being achieved.
In conventional clock generating circuit 1500, stabilization of oscillation circuit 1510 is determined by counting the clock OSCCLK1 directly with exclusive counter 1522. However, when the reset is cancelled, as oscillation starts, an oscillating frequency provided by oscillation circuit 1510 may be undesirably high. Thus, depending upon how high a frequency is being output, a resulting count may not be correctly conducted. As a result, a time difference may occur between when the oscillation circuit 1510 is actually stabilized and when output Q of flip-flop 1524 goes high to enable the generation of clock CLK. Such a variation can cause an erroneous generation of clock CLK.
In conventional clock generating circuit 1700, the oscillation circuit 1720 is operated by providing a voltage provided by voltage regulator 1722 to lower power consumption when the oscillation of oscillation circuit 1720 is stabilized. However, RC circuit 1710 can require a large capacitor and resistor external to the chip. These external components increase costs. Also, the values of the capacitor and resistors may need to be tuned in accordance with the device operating parameters.
That is, RC circuit 1710 is provided to a reset terminal external to the chip in order to provide a time delay to ensure that oscillation circuit 1730 is stabilized. Such a delay is dependent upon a time constant of such an RC circuit. However, to ensure a sufficient time delay until oscillation circuit 1730 is stabilized, a very large capacitor and resistor can be required. This can increase manufacturing costs and therefore the cost to the customer is increased. Further, because the time period until the oscillation circuit 1730 is stabilized may vary between use methods and device samples, the capacitor and resistor must be specifically tuned.
In conventional clock generating circuit 1100, even if a Schmidt trigger inverter is used as buffer circuit 1140, an incorrect oscillation in the vicinity of the threshold value may not be distinguished from a correct oscillation. This is because the Schmidt trigger inverter operates even when an incorrect oscillation is made. As a result, the counter 1120 may receive an input caused by such an incorrect oscillation. In this way, the time period provided to ensure the oscillation of oscillation circuit 1110 to become stabilized can be adversely affected.
Also, conventional clock generating circuits (900 and 1700) provide a time delay not based on the output of oscillation circuits. Thus, the time period provided to ensure oscillation stabilization may be unnecessarily long and a time delay before proper operation may increase. Accordingly, because the time period until the oscillation is stabilized is not practically detected but instead experimentally predicted, a time delay must be set in accordance with a worst case condition.
In view of the above discussion, it would be desirable to provide a clock generating circuit that may have low power consumption when an oscillating circuit and a logic circuit operates when compared with conventional approaches.
It would also be desirable to provide a clock generating circuit that can provide a shorter oscillation stabilization wait time than conventional approaches. It would also be desirable to provide a clock generating circuit which may provide a shorter oscillation stabilization wait time with reduced adverse affects due to variation in characteristics of an oscillating element or the like.
It would also be desirable to provide a clock generating circuit which may provide a shorter oscillation stabilization wait time and may provide a timing for automatically switching an oscillating circuit and/or an internal logic circuit from an external power supply voltage to a reduced voltage supply.
It would also be desirable to provide a clock generating circuit which may be capable of preventing a system with an oscillating circuit from supplying an oscillation clock to an internal logic circuit when the oscillation clock is unstable to thereby reduce system malfunctions.